The present invention relates to a method and circuit for processing digital signal representative of vectors or tuples of the same dimension and application thereof to cardinality sets and to vectors or tuples of any dimensions.
In the field of scientific computation, the processing of digital signals representative of vectors or tuples is at the present time based on the use of supercomputers working at a high rate but sequentially on the data to be processed. More generally, vectorial or parallel machines or machines known as "array processors" are used. For using high specialized computing powers implanted in one or more VLSI circuits, systolic type architectures have been proposed for general purpose machines, such as the machine proposed by the Carnegie Mellon Institute in the US under the name WARP and the derived integrated circuit announced by the firm INTEL under the name iWARP.
Among circuits with systolic type architecture there may be further mentioned the neuronal networks which have given rise to monodimensional architectures of the above type (SY Kung).
For implementing data bases of other circuit architectures there have been proposed, in particular, the architecture designated under the name of RAPID which forms the subject of the patent application U.S. 061 642 in the names of P. Fandemay, D. Etiemble and H. He.
The above solutions of the prior art based either on the use of numerous dedicated circuits working in parallel or on the use of super computers requiring a large number of processors and high performance memories lead to very expensive solutions. With the growing increase in the degree of integration, at the present time computing powers corresponding to several milliard specialized operations per second can be currently implanted on a single circuit, by coupling numerous processors in parallel inside a circuit.
These circuits, in order to operate, need to be fed both with operands and/or coefficients. When the coefficients are reduced in number and when the data is re-used a large number of times, as in filtering applications for example, architectures with internal storage base and systolic structures are suitable solutions.
The problem arises on the other hand when the size of the data processing objects to be processed, table or list, increases and when consequently it becomes ineffectual even impossible to store the coefficients or data internally, i.e. in the circuit itself.
If it is then desired to feed the computing processors which can be placed in one of said circuits, it is necessary to increase the communication rate with the external memories by increasing the number of connecting lugs of the circuit and the connection and exchange frequency with these memories.
Apart from said solution, it is possible to use memories hidden in these circuits.
However, the limitations of the corresponding present-day solutions are due to a poor organization of the computations which leads, because of poor balancing, to time "overheads" or overshoots, or to a loss of efficiency in the computing power installed or to an increase of the storage area required, which, in the last resort, often causes under use of the resources.